Contact us | Sitemap | English
       
 
Design (RTL)
Frontend
Backend
 
About u

아르고는 숙련된 High Speed/Low Power/HPDF Design 경험을 바탕으로 최적의 Physical Design Implementation Service 를 지원하며, Emerging Design Quality Issue를 반영하여 Highest Quality of Silicon 을 제공해 드립니다.

Emerging Design Quality Issue
Chip Size / Yield / IR-Drop, Rise / IVD / Electro Migration / Signal Integration / On Chip Variation / Temperature / High Frequency / Delay / OPC / DFM, DFY / Shielding / Multi-Corner



gototop
 
FloorPlan   PowerPlan   Placement   CTS   Route  
FloorPlan  
  • Specifies the design’s die size for low cost
  • Estimates the congestion for design routable
  • Estimates the parasitic for delay calculation
  • Analysis power for reliability
 
gototop
 
FloorPlan   PowerPlan   Placement   CTS   Route  
PowerPlan  
  • Add core, block ring
  • Add Stripes over Macro within the overall design
  • Routing standard cell pins
  • Lower Power Aware
  • Bump Arrays & RDL Routing for Flip-Chip Design
 
gototop
 
FloorPlan   PowerPlan   Placement   CTS   Route  
Placement  
  • Timing and congestion consideration during placement
  • Places the spare cells within the overall core area
  • places JTAG cells around the periphery of the core area
  • Logic Optimization can include the following operations
   - Adding buffers
   - Cell Sizing
   - Logic restructuring
   - Remapping logic
   - Swapping pins
   - Deleting buffers
   - Moving instances
 
gototop
 
FloorPlan   PowerPlan   Placement   CTS   Route  
CTS  
  • The goal of CTS is to minimize skew and phase delay
  • For Performance and stability of a synchronized system, we need an efficient Clock Tree Synthesis methodology to design clock distribution network. In a system-on-chip(SOC) design environment, CTS effectively distributes clock signals from clock sources to synchronized points on layout design.
 
gototop
 
FloorPlan   PowerPlan   Placement   CTS   Route  
Route  
  • Routing is the process of creating physical connections based on logical connectivity
  • Routing considered Signal Integrity, timing, design for yield and also physical DRC requirements
  • The SI Driven routing reduced coupling capacitance by spreading adjacent wires.
  • The router reduces coupling capacitance by
   - Spreading wires apart
   - Changing metal layers
   - Minimizing parallel long wire
   - Buffer insertion
   - Shielding
 
gototop
 
Verification  
  • ANT
   - Antenna Rule Check
  • DRC (Design Rule Check)
   - Run Verify Tool for Design Rule Checkin
  • LVS (LAYOUT Versus Schematic)
   - Compare LAYOUT with Schematic
 

 

gototop
 
주식회사 아르고  TEL : 031)713-0607  FAX : 031)713-0207  e-mail : support@argosys.co.kr
Copyright ⓒ ARGO Co.,LTD. All rights reserved.