The goal of CTS is to minimize skew and phase delay
For Performance and stability of a synchronized system, we need an efficient Clock Tree Synthesis methodology to design clock distribution network. In a system-on-chip(SOC) design environment, CTS effectively distributes clock signals from clock sources to synchronized points on layout design.
Routing is the process of creating physical connections based on logical connectivity
Routing considered Signal Integrity, timing, design for yield and also physical DRC requirements
The SI Driven routing reduced coupling capacitance by spreading adjacent wires.
The router reduces coupling capacitance by
- Spreading wires apart
- Changing metal layers
- Minimizing parallel long wire
- Buffer insertion
- Antenna Rule Check
DRC (Design Rule Check)
- Run Verify Tool for Design Rule Checkin
LVS (LAYOUT Versus Schematic)
- Compare LAYOUT with Schematic
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