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Design Flow
HPDF
Low Power Design
Signal Integrity
 
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It is obvious that the necessity and technology of Low Power Design in SoC design is an extremely important issue. Especially Low Power / High Performance is necessary to mobile products such as Smart Phone, Notebook, and Tablet PCs, and technologies to decrease and manage power consumption are applied. ARGO helps customers to have satisfying design and power spec. using its know-how and guide regarding low power design. In addition, it is continuously developing low power design technology.
Clock Gating
Clock Gating efficiently decreases the dynamic power of relevant logic by turning the Register Group Clock On/Off.
Multi-Vth
By using Multiple Vth Library where Low Vth Cell with small cell delay is only used at timing critical paths and High Vth Cell with small leakage power is used for other paths, the total power consumption can be decreased.
Power Gating
This method decreases power consumption by controlling the inner power switch of the block that does not operate inside the chip. Switch Cell, Isolation Cell, Retention Register, and Always On Cell are used and Power Control Module must be designed separately that turns the Switch Cell on/off inside.
Multi-Vdd
Low supply voltage is applied to blocks that work with low speed and high speed blocks are given high supply voltage, thereby decreasing unnecessary power consumption through low speed blocks.
 
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